W9812G2GH-6C - a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words × 4 banks × 32 bits 

1 GENERAL DESCRIPTION 

W9812G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 

1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, 

W9812G2GH delivers a data bandwidth of up to 166M words per second (-6). For different application, 

W9812G2GH is sorted into two speed grades: -6/-6C/-6I and -75. The –6 is compliant to the 

166MHz/CL3 specification and –6C/-6I is tIH=0.8nS. The -75 is compliant to the 133MHz/CL3 

specification. 

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be 

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE 

command. Column addresses are automatically generated by the SDRAM internal counter in burst 

operation. Random column read is also possible by providing its address at each clock cycle. The 

multiple bank nature enables interleaving among internal banks to hide the precharging time. 

By having a programmable Mode Register, the system can change burst length, latency cycle, 

interleave or sequential burst to maximize its performance. W9812G2GH is ideal for main memory in 

high performance applications. 

2 FEATURES 

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3.3V ± 0.3V Power Supply 

Up to 166 MHz Clock Frequency 

1,048,576 Words × 4 banks × 32 bits organization 

Self Refresh Mode 

CAS Latency: 2 and 3 

Burst Length: 1, 2, 4, 8 and full page 

Burst Read, Single Writes Mode 

Byte Data Controlled by DQM 

Auto-precharge and Controlled Precharge 

4K Refresh cycles / 64 mS 

Interface: LVTTL 

Packaged in TSOP II 86 pin, 400 mil – 0.50 

W9812G2GH is using Lead free materials with RoHS compliant

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