K4J52324QC-BC14
512Mbit GDDR3 SDRAM
FEATURES
• 2.0V + 0.1V power supply for device operation for -BJ**
• 2.0V + 0.1V power supply for I/O interface for -BJ**
• 1.8V + 0.1V power supply for device operation for -BC**
• 1.8V + 0.1V power supply for I/O interface for -BC**
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• 1.8V Pseudo Open drain compatible inputs/outputs
• 4 internal banks for concurrent operation
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock)
• Additive latency (AL): 0 and 1 (clock)
• Programmable Burst length : 4 and 8
• Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh modes
• Auto Precharge option
• 32ms, auto refresh (8K cycle)
• 136 Ball FBGA
• Maximum clock frequency up to 800MHz
• Maximum data rate up to 1.6Gbps/pin
• DLL for outputs
• Boundary scan function with SEN pin
• Mirror function with MF pin
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批發(fā)與零售價(jià)位不同,無法一一明示,詳情請(qǐng)通過郵件或客服咨詢(國內(nèi)銷售部電話:0755-83957301,企業(yè)QQ2850151585), 由于電子元器件價(jià)格不穩(wěn)定,時(shí)常有稍許變動(dòng),本公司未能及時(shí)調(diào)整,如您覺得售價(jià)不適,請(qǐng)與我們說明并適當(dāng)議價(jià),謝謝支持。