Features
• Low-cost, register/latch rich, SRAM based reprogrammable architecture
- 0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRing™ I/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution nets
• Versatile I/O and Packaging
- Innovative VersaRing™ I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies system timing
- Independent Output Enables for external bussing
- Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series
- Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available
• Fully Supported by Xilinx Development System
- Automatic place and route software
- Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
- Supported by shrink-wrap Foundation software
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【買家必讀】:電子元器件是專業(yè)型的產(chǎn)品,技術(shù)含量較高,本身可能存在多種品牌,後輟與封裝,可能導(dǎo)致參數(shù)與性能的差異,如有不慎,很有可能導(dǎo)致元器件購(gòu)買錯(cuò)誤,為了更好的解決您的問題,所以請(qǐng)您務(wù)必在下單前,將產(chǎn)品的封裝、後綴告訴我們。以便我們能準(zhǔn)確迅速的為您查詢。。
由于客戶采購(gòu)批量與樣品的價(jià)格不同,網(wǎng)上無(wú)法統(tǒng)一注明,請(qǐng)您把采購(gòu)型號(hào)通過頁(yè)面旺旺或客服QQ401799895或撥打國(guó)內(nèi)銷售部電話:0755-83957301,由客服人員為您報(bào)價(jià);有時(shí)元件廠商價(jià)格稍許變動(dòng),本公司未能及時(shí)調(diào)整,如您覺得售價(jià)稍高,請(qǐng)與我們說明并適當(dāng)議價(jià),我們會(huì)根據(jù)市場(chǎng)情況給您相應(yīng)的折扣,我們保證提供最市場(chǎng)最優(yōu)勢(shì)的價(jià)格最好元器件;感謝支持(所售元件均無(wú)含稅,需開普票7%和增值票17%的客戶請(qǐng)說明)
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