TLK2501IRCP  -1.5 TO 2.5 GBPS TRANSCEIVER

description

The TLK2501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed

bidirectional point-to-point data transmission systems. The TLK2501 supports an effective serial interface

speed of 1.5 Gbps to 2.5 Gbps, providing up to 2 Gbps of data bandwidth. The TLK2501 is pin-for-pin compatible

with the TLK2500. The TLK2501 is both pin-for-pin compatible with and functionally identical to the TLK1501,

a 0.6 to 1.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of

performance solutions with no required board layout changes.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband

data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be

printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is

dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the

number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter

is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance

backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power

and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK2501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions

as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.5 Gbps.

The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The

16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The

resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The

receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit

wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using

8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The

outcome is an effective data payload of 1.20 Gbps to 2.0 Gbps (16 bits data x the GTX_CLK frequency).

The TLK2501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use

of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which

has an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is

recommended that the TLK2501 PowerPAD is soldered to the thermal land on the board. All ac performance

specifications in this data sheet are measured with the PowerPAD soldered to the test board.

Hot-Plug Protection

1.5 to 2.5 Gigabits Per Second (Gbps)

Serializer/Deserializer

High-Performance 64-Pin VQFP Thermally

Enhanced Package (PowerPAD?)

2.5-V Power Supply for Low Power

Operation

Programmable Voltage Output Swing on

Serial Output

Interfaces to Backplane, Copper Cables, or

Optical Converters

Rated for Industrial Temperature Range

On-Chip 8-Bit/10-Bit (8B/10B)

Encoding/Decoding, Comma Alignment,

and Link Synchronization

On-Chip PLL Provides Clock Synthesis

From Low-Speed Reference

Receiver Differential Input Thresholds

200 mV Minimum

Typical Power: 360 mW

Loss of Signal (LOS) Detection

Ideal for High-Speed Backplane

Interconnect and Point-to-Point Data Link

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