ISPLSI1032E-70LJ
In-System Programmable High Density PLD
Features
HIGH DENSITY PROGRAMMABLE LOGIC
6000 PLD Gates
64 I/O Pins, Eight Dedicated Inputs
192 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
Small Logic Block Size for Random Logic
HIGH PERFORMANCE E2
CMOS®
TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
In-System Programmable (ISP™) 5V Only
Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Complete Programmable Device Can Combine Glue
Logic and Structured Designs
Enhanced Pin Locking Capability
Four Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control to
Minimize Switching Noise
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
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