XC5202-6VQ100C -- XC5200 Series Field Programmable Gate Arrays
Features
• Low-cost, register/latch rich, SRAM based reprogrammable architecture
- 0.5µm three-layer metal CMOS process technology
- 256 to 1936 logic cells (3,000 to 23,000 “gates”)
- Price competitive with Gate Arrays
• System Level Features
- System performance beyond 50 MHz
- 6 levels of interconnect hierarchy
- VersaRing™ I/O Interface for pin-locking
- Dedicated carry logic for high-speed arithmetic functions
- Cascade chain for wide input functions
- Built-in IEEE 1149.1 JTAG boundary scan test circuitry on all I/O pins
- Internal 3-state bussing capability
- Four dedicated low-skew clock or signal distribution nets
• Versatile I/O and Packaging
- Innovative VersaRing™ I/O interface provides a high logic cell to I/O ratio, with up to 244 I/O signals
- Programmable output slew-rate control maximizes performance and reduces noise
- Zero Flip-Flop hold time for input registers simplifies system timing
- Independent Output Enables for external bussing
- Footprint compatibility in common packages within the XC5200 Series and with the XC4000 Series
- Over 150 device/package combinations, including advanced BGA, TQ, and VQ packaging available
• Fully Supported by Xilinx Development System
- Automatic place and route software
- Wide selection of PC and Workstation platforms
- Over 100 3rd-party Alliance interfaces
- Supported by shrink-wrap Foundation software
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