PI7C21P100 - 2-PORT PCI-X BRIDGE - Pericom Semiconductor Corporation
FEATURES
- INDUSTRY STANDARDS COMPLIANCE
PCI-X Addendum to the Local Bus Specification Revision 1.0a (Mode 1 only)
PCI Local Bus Specification Revision 2.2
PCI-to-PCI Bridge Architecture Specification Revision 1.1
PCI Power Management Interface Specification Revision 1.1
• Supports D0 and D3 power states
- INTERFACE
3.3V signaling with 5V tolerance
133MHz / 64-bit operation on both buses
Dual address cycle support
Concurrent primary and secondary bus operation
Primary and secondary may be run in either PCI mode or PCI-X Mode 1
Asynchronous operation support
Programmable internal arbiter with support for up to 6 external masters on the
secondary bus
• Internal arbiter may be disabled to use an external arbiter
IEEE 1149.1 JTAG support
- OPERATION
Type 0 and Type 1 configuration support
Configuration register access from both primary and secondary buses
2KB of buffering for upstream memory burst read commands
2KB of buffering for downstream memory burst read commands
1KB of buffering for upstream posted memory write commands
1KB of buffering for downstream posted memory write commands
Support for up to 8 active transactions in each direction
- ADDITIONAL FEATURES
Capabilities pointer
Ability to define an opaque memory address
Definable base address register
Secondary side PCI-X device privatization
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