TMS320VC33PGE

DIGITAL SIGNAL PROCESSOR

High-Performance Floating-Point Digital

Signal Processor (DSP):

TMS320VC33-150

13-ns Instruction Cycle Time

150 Million Floating-Point Operations

Per Second (MFLOPS)

75 Million Instructions Per Second

(MIPS)

TMS320VC33-120

17-ns Instruction Cycle Time

120 MFLOPS

60 MIPS

34K × 32-Bit (1.1-Mbit) On-Chip Words of

Dual-Access Static Random-Access

Memory (SRAM) Configured in 2 × 16K Plus

2 × 1K Blocks to Improve Internal

Performance

x5 Phase-Locked Loop (PLL) Clock

Generator

Very Low Power: < 200 mW @ 150 MFLOPS

32-Bit High-Performance CPU

16-/32-Bit Integer and 32-/40-Bit

Floating-Point Operations

Four Internally Decoded Page Strobes to

Simplify Interface to I/O and Memory

Devices

Boot-Program Loader

EDGEMODE Selectable External Interrupts

32-Bit Instruction Word, 24-Bit Addresses

Eight Extended-Precision Registers

On-Chip Memory-Mapped Peripherals:

One Serial Port

Two 32-Bit Timers

Direct Memory Access (DMA)

Coprocessor for Concurrent I/O and CPU

Operation

Fabricated Using the 0.18-µm (leff

-Effective

Gate Length) TImeline? Process

Technology by Texas Instruments (TI)

144-Pin Low-Profile Quad Flatpack (LQFP)

(PGE Suffix)

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

Two Low-Power Modes

Two- and Three-Operand Instructions

Parallel Arithmetic/Logic Unit (ALU) and

Multiplier Execution in a Single Cycle

Block-Repeat Capability

Zero-Overhead Loops With Single-Cycle

Branches

Conditional Calls and Returns

Interlocked Instructions for

Multiprocessing Support

Bus-Control Registers Configure

Strobe-Control Wait-State Generation

1.8-V (Core) and 3.3-V (I/O) Supply Voltages

On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG)

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