Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

 

 

 

Features

 VDD/VDDQ = 1.70–1.95V

 Bidirectional data strobe per byte of data (DQS)

 Internal, pipelined double data rate (DDR) 

architecture; two data accesses per clock cycle

 Differential clock inputs (CK and CK#)

 Commands entered on each positive CK edge

 DQS edge-aligned with data for READs; centeraligned with data for WRITEs

 Four internal banks for concurrent operation

 Data masks (DM) for masking write data—one mask 

per byte

 Programmable burst lengths: 2, 4, or 8

 Concurrent auto precharge option supported

 Auto refresh and self refresh modes

 1.8V LVCMOS compatible inputs

 On-chip temperature sensor to control self refresh 

rate

 Partial-array self refresh (PASR)

 Deep power-down (DPD)

 Selectable output drive (DS)

 Clock stop capability

 64ms refresh period

 

 

 

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