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FEATURES
Two scalable 64-bit MIPS CPUs
600 MHz–800 MHz
Quad-issue in order pipeline; dual execute, dual memory pipes
Enhanced skew pipeline enables zero load-to-use penalty
32-KB instruction cache, 32-KB data cache
Advanced branch predictors
Fast, on-chip multiprocessor bus
Connects the CPUs, L2 cache, memory controller and I/O bridges
Runs at half the CPU core frequency; 256 bits wide
On-chip L2 cache
512 KB, shared by both CPUs
4-way associative, ECC protected
Ways can be removed to provide fast on-chip RAM
DDR memory controller
wo channels, each with a 64-bit data bus plus optional ECC
Runs up to 200 MHz clock rate, 400 MHz data rate
Support for DDR SDRAM, SGRAM, and FCRAM
High-speed packet interfaces
Three 10/100/1000 Ethernet MACs; 802.3 compliant
Option to configure MACs into packet FIFOs
Up to two packet FIFOs each capable of OC-48 data rates
PCI interface
32 bits, 33/66 MHz (PCI 2.2)
Host bridge or target device
HyperTransport™ (formerly LDT) I/O interface
Complies with HyperTransport standard for high-speed I/O fabric
500-MHz clock rate, double data rate, for 600-MHz CPUs; 600-MHz
clock rate for 800-MHz CPUs
Peak bandwidth of 9.6 Gbps in each direction @ 600 MHz
Supports double-ended fabrics (to link two BCM1250s)
Integrated system I/O
Generic I/O for direct connect to boot ROM, flash
Two SMBus serial configuration interfaces
PCMCIA control interface
Two serial interfaces
Extensive, on-chip debug features
8–10W power dissipation @ 800 MHz
Support for leading operating systems including VxWorks®, Linux®
and NetBSD
Evaluation board platform available with tools, firmware and software
drivers
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