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EP2S60F484I4

EP2S60F484I4
型號(hào):EP2S60F484I4
品牌:Altera Altera
批號(hào):13+
封裝:BGA
原價(jià):2000
數(shù)量:45870
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 EP2S60F484I4 Datasheet (PDF) - Altera Corporation

 
 
■ 15,600 to 179,400 equivalent LEs; see Table 1–1
■ New and innovative adaptive logic module (ALM), the basic 
building block of the Stratix II architecture, maximizes performance 
and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without 
reducing logic resources
■ TriMatrix 
memory consisting of three RAM block sizes to implement 
true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of 
multipliers (at up to 450 MHz), multiply-accumulate functions, and 
finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, 
which allows clock networks to power down to reduce power 
consumption in user mode
 
 
 
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