FEATURES

An accelerated 80C51 CPU provides instruction cycle times of

300–600ns for all instructions except multiply and divide when

executing at 20 MHz. Execution at up to 20 MHz when

VDD = 4.5 V to 6.0 V, 10 MHz when VDD = 2.7 V to 6.0 V.

2.7 V to 6.0 V operating range for digital functions.

2 kbytes EPROM code memory.

128 byte RAM data memory.

32-byte customer code EPROM allows serialization of devices,

storage of setup parameters, etc.

Two 16-bit counter/timers. Each timer may be configured to toggle

a port output upon timer overflow.

Two analog comparators.

Full duplex UART.

I2C communication port.

 

 

 

 

 

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