GAL6002B-15LP - High Performance E2CMOS FPLA Generic Array Logic - Lattice Semiconductor
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
15ns Maximum Propagation Delay
75MHz Maximum Frequency
6.5ns Maximum Clock to Output Delay
TTL Compatible 16mA Outputs
UltraMOS®
Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL PINS
LOW POWER CMOS
90mA Typical Icc
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
UNPRECEDENTED FUNCTIONAL DENSITY
78 x 64 x 36 FPLA Architecture
10 Output Logic Macrocells
8 Buried Logic Macrocells
20 Input and I/O Logic Macrocells
HIGH-LEVEL DESIGN FLEXIBILITY
Asynchronous or Synchronous Clocking
Separate State Register and Input Clock Pins
Functional Superset of Existing 24-pin PAL®
and FPLA Devices
APPLICATIONS INCLUDE:
Sequencers
State Machine Control
Multiple PLD Device Integration
**注意 & Noted:
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