■ Separate Independent Read and Write Data Ports

? Supports concurrent transactions

■ 333 MHz Clock for High Bandwidth

■ 2-word Burst on all Accesses

■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 666 MHz) at 333 MHz 

■ Two Input Clocks (K and K) for precise DDR timing

? SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems

■ Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW

■ Available in x8, x9, x18, and x36 Configurations 

■ Full Data Coherency, providing Most Current Data

■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD

? Supports both 1.5V and 1.8V IO supply

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

 

格式 - 存儲器	RAM
存儲器類型	SRAM - 同步，QDR II
存儲容量	72M（4M x 18）
速度	250MHz
接口	并聯(lián)
電壓 - 電源	1.7 V ~ 1.9 V
工作溫度	-40°C ~ 85°C
封裝/外殼	165-LBGA

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