CY7C1474 CY7C1474V25 CY7C1474V25-200BGI -- 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V/1.8V I/O supply (VDDQ)
• Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V25, CY7C1472V25 available in JEDEC-standard lead-free 100-pin TQFP, lead-free and non-lead-free 165-ball FBGA package. CY7C1474V25 available in lead-free and non-lead-free 209 ball FBGA package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
包裝 |
托盤 |
存儲器類型 |
SRAM - 同步 |
存儲容量 |
72M(1M x 72) |
封裝/外殼 |
209-BGA |
工作溫度 |
-40°C ~ 85°C |
接口 |
并聯 |
格式 - 存儲器 |
RAM |
電壓 - 電源 |
2.375 V ~ 2.625 V |
速度 |
200MHz |
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