CY7C1414 CY7C1414KV18 CY7C1414KV18-300BZXC -- 36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports
? Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ 2-word burst on all accesses
■ Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
? SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Single multiplexed address input bus latches address inputs for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW
■ Available in × 8, × 9, × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
? Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
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