9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture

 

 

Features

Pin-compatible and functionally equivalent to ZBT™

Supports 250-MHz bus operations with zero wait states

Available speed grades are 250, 200, and 166 MHz

Internally self-timed output buffer control to eliminate 

the need to use asynchronous OE

Fully registered (inputs and outputs) for pipelined 

operation

Byte Write capability

Single 3.3V power supply (VDD)

3.3V or 2.5V I/O power supply (VDDQ)

Fast clock-to-output times

2.8 ns (for 250-MHz device)

Clock Enable (CEN) pin to suspend operation

Synchronous self-timed writes

Available in lead-free 100-Pin TQFP package, lead-free 

and non lead-free 119-Ball BGA package and 165-Ball 

FBGA package

IEEE 1149.1 JTAG-Compatible Boundary Scan

Burst capability–linear or interleaved burst order

“ZZ” Sleep Mode option and Stop Clock option

 

 

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