CY7C1250 CY7C1250KV18 CY7C1250KV18-400BZXC -- 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 450 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
? SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
? Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
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