SAA7709H - Car radio Digital Signal Processor DSP

In Table 2 the port pinning is depicted. This equalizer

accelerator circuit (EQ) can make a two-channel equalizer

of 10 second-order sections per channel or a four-channel

equalizer of 5 second-order sections per channel

depending on the value of AD register bit TWO-FOUR

(see Table 9). It takes an input sample set of 2 (stereo)

samples or 4 (stereo front and rear) samples via 4 input

registers. It delivers an output sample set of 2 or

4 samples via 4 output registers. All input and output

registers are 18 bits wide.

A pulse of three clock cycles long of the signal start based

on the word select of the used signal path refreshes the

EQ input and output registers and starts up the EQ

controller.

This sequence is shown in Fig.8.

8.5.3 CONTROLLER AND PROGRAMMING CIRCUIT

A controller is used to generate the bit control and

word control signals for the filter section data path, the

addresses for the coefficient memory and the control

signals for the input and output selections and

conversions. Depending on the AD register

bit TWO-FOUR (see Table 9), control signals for a two- or

four-channel equalizer are generated.

The 40 coefficient words should be addressed via

40 registers (addresses 0F80H to 0FA7H).

The new coefficient word rate must be slower than 0.5fs,

e.g. 22 kHz. The equalizer is programmed by dedicated

software. 

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